Since the development of the integrated circuit (IC), the semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. The continued reduction in minimum feature size has been accompanied by challenges.
In the fabrication of these ICs, processes typically include the deposition of various materials. Some of the depositions may be by using a high density plasma (HDP) chemical vapor deposition (CVD). With the reduction in minimum feature size, the HDP-CVD process has encountered problems. The HDP-CVD process may have poor uniformity of deposition for small technology nodes and, thus, may have a process window limit for corresponding hardware.
Previous attempts to solve these problems include a trial and error process where nozzles within a tool would be adjusted to control the deposition. However, this typically caused other problems. The trial and error process typically required the tool to be opened to have the nozzles adjusted. This required significant down time for the tool. Thus, these previous attempts wasted available tool time that could have been used to process wafers. Further, by having the tool opened, the tool would possibly be exposed to contaminants, and the continuous adjusting of parts could decrease the useful life of those parts necessitating increased parts costs.
Accordingly, a better solution to allow for the use of plasma processes at smaller technology nodes is needed to aid in the further reduction of minimum feature size.